In semiconductor integrated circuits, smaller minimum feature size regimes (generally limited by lithographic resolution) and greater integration densities have been continually sought in order to reduce signal propagation time and increase switching clock rates as well as to improve noise immunity. High integration density also allows more functionality to be provided on a chip of given dimensions as well as substantial economy in manufacture to develop a given level of functionality. However, semiconductor integrated circuits based on transistor switches are approaching the theoretical limits on minimum feature size and maximum integration density. Further, increases in integration density and switching clock rates are requiring operation at very low voltages and currents in order to reduce heat dissipation requirements for logic circuits and so-called support circuits in storage devices operated at high clock rates. Even when the vast majority of transistors on a chip are formed at minimum feature size and operated at low voltages and currents, a substantial number of transistors on the chip must be formed at larger sizes and operated at higher voltages and currents for particular purposes such as input/output (I/O) drivers, on-chip voltage regulators, drivers for busses and large fan-out logic circuits and the like.
A particular problem is presented by the fact that many integrated circuit logic devices such as microprocessors require some storage which can be accessed in a very few extremely short clock cycles and thus the storage must be supplied on the chip. At the current state of the art, such storage for changeable data is provided as dynamic random access memory (DRAM) or static random access memory (SRAM) which are very different structures with very different properties. DRAM cells generally comprise only a small capacitor structure and a single transistor which can generally be formed substantially above the capacitor. Therefore, the memory cells can be very small and integration density is generally governed by the spacing between the capacitors that is needed for adequate isolation. However, such memory structures require refreshing at frequent intervals since the amount of change stored on a given capacitor structure is very small and the transistors as well as the capacitor structures are subject to leakage. Refresh operations can occupy a significant portion of the operation time of the DRAM and can limit access time. Sensing of the stored charge also requires a significant amount of time since such sensing is generally performed by using the stored charge (or lack of stored charge) to unbalance a bistable circuit which has been balanced between stable states and, after a read operation, the memory cell state must be rewritten. Therefore, response time of a DRAM is relatively slow.
Where memory response time is critical and must be performed rapidly, SRAMs are generally employed. Instead of storing data as charge on a capacitor structure as in DRAM cells, an SRAM cell is formed as a bistable transistor circuit, generally by cross-coupling the outputs and inputs of a pair of inverter circuits and including an additional pair of transistors for memory cell selection. Therefore such SRAM cells can be formed using four (with two additional passive resistors in the inverter circuits), six or eight transistors or more which infers a significant increase in chip area occupied by an SRAM cell. Additionally, in practice, the wiring to provide the cross-coupling of the inverters and the preferred orientation of the transistors (to have the conduction paths in the same direction for more uniform conduction characteristics) requires substantial further chip space. A layout for a six transistor SRAM cell that is considered optimally compact thus requires ten top twelve time the area required for a single transistor, which, as alluded to above, appears to be reaching the practical limits of size reduction.
There has also been continuing interest in non-volatile memories which are devices that can retain stored information substantially indefinitely without power being applied. This capability provides substantial advantage in terms of convenience and/or security since data, once written, is permanently stored on a device independently of any power supply which may be lacking or subject to power interruption such as discharge or changing of batteries in portable devices. So-called floppy disks were an early expedient for providing such a function but were limited in storage capacity while being somewhat larger than might be convenient and subject to damage. Optical disks provided greater storage capacity but were also relatively large and, like floppy disks, required a complex and expensive device for reading stored data while having the disadvantage of not providing for data to be changed.
More recently semiconductor-based non-volatile memories have been developed that are much smaller and can be read electronically without requiring a reading device. Such devices have been used widely in electronic devices such as digital cameras, cellular telephones and music players as well as in general computer systems, embedded systems and other devices that require persistent storage. Such devices often take the form of removable and portable memory cards and storage capacities of tens of gigabytes are available at low cost. However, semiconductor-based non-volatile memories such as flash memories and electrically erasable programmable read only memories (EEPROMs) require semiconductor structures and operations which are of limited scalability and integration density and not optimal in speed and are thus not well-suited to some applications.
Therefore, other types of structures are being investigated as potential alternatives to transistors for memory cells and some logic circuits, in particular, devices that can store data as differing resistance. Among these devices is a so-called phase change RAM (PCRAM) using a chalcogenide element as a variable resistor and a resistance RAM (ReRAM) that uses a transition metal oxide element. One structure that has been proposed in the last few years is a conductive bridge RAM (CBRAM) based on a capacitor-like structure also developed in recent years and sometimes referred to as a memristive switch or an ionic or atomic switch which changes resistance by precipitating metal cations to form a conductive bridge and ionizing the precipitated metal to destruct the bridge. The capacitor-like structure comprises two opposed plates of differing materials (e.g. metals) with a dielectric material between them that also exhibits electrolytic properties. One of the opposed plates is of an oxidizable material or metal (referred to as active) such as copper or silver and the other of a substantially inert conductive material or metal such as platinum or tungsten. A suitable dielectric material having electrolytic properties is tantalum oxide such as Ta2O5 or an oxygen deficient form thereof denoted by TaOx. Such a structure is initially non-conductive. However, when a suitable bias voltage is applied to the respective opposed plates, ions of the active metal (e.g. Cu+) are extracted from the active metal plate and drift-diffuse through the electrolyte and are stopped by and accumulate on the inert electrode. As ion drift-diffusion continues, active metal builds up on the inert electrode forming filaments (sometimes referred to as nanofilaments) that eventually reach the active metal electrode and the device abruptly becomes conductive. This process is reversible, causing the nanofilaments to rupture, returning some of the active metal ions to the active metal electrode and returning the switch to a non-conductive state, and, depending on the active metal and electrolyte, exhibits sharply defined voltage thresholds at which the conductive filament formation occurs.
As alluded to above, a structure comprising two such atomic switches formed back-to-back such that only a single inert electrode which can be allowed to electrically float is provided in common for both atomic switches has been proposed as a non-volatile memory (NVM) cell or logic circuit that does not require transistors as part of the storage structure. This structure is referred to as a resistive, floating inert electrode device or RFED. The potential for miniaturization is clear since it is only required that some finite but arbitrarily small area be provided and the two atomic switches can preferably be formed in a vertical orientation (the respective atomic switches being then referred to as upper and lower switches; a convention that will be used hereinafter for convenience but without any inference of relative orientation of the atomic switches being intended) and theoretically provide four electrical states (e.g. two different resistive states for each atomic switch) corresponding to two bits of information.
However, three of these states (e.g. where no nanofilaments are formed in either atomic switch or nanofilaments are formed in only one of the atomic switches) are difficult to distinguish in a two terminal device since all three states are of high impedance and the switch in which nanofilaments are formed (or ruptured) cannot be discriminated. Further, as proposed, such RFEDs cannot be formed as arrays where connection of RFEDs may cause so-called sneak circuits to other RFEDs through the inert electrode or dielectric electrolyte. Such sneak circuits can also be caused in an array of RFEDs fabricated in an optimally compact cross-bar configuration by the easily distinguishable fully conductive state where nanofilaments exist in both atomic switches of an RFED. Additionally, relatively strong electric fields are required to cause sufficient electromigration or drift-diffusion to form or rupture nanofilaments. Also, as a practical matter, volatility/persistence of storage is relatively unstable; tending to vary with the past writing history of the individual RFED cell. By the same token writing operation to an RFED cell may require extended highly variable periods of time; again depending on the previous storage state of the RFED cell. The RFED cell also tends to generate pulses if the set and reset thresholds present only a small operating window. In conventional circuitry, a large number of transistors is needed to generate a current or voltage pulse. With an RFED, only one highly scalable device is needed. Due to at least these problems which have been largely intractable, RFEDs have not been widely studied or developed. Therefore, at the current state of the art, RFEDs do not provide a practical alternative to transistors in logic circuits and storage devices.